The junction field-effect transistor — the JFET — is the quiet member of the transistor family. Unlike a BJT it needs no base current, and unlike a MOSFET it has no fragile oxide layer. Its gate is a reverse-biased pn junction, so it draws essentially no current, and its drain current is controlled purely by the gate voltage. This post explains the JFET with a worked self-biased amplifier design.

Figure 1: The self-biased JFET amplifier (a) and its transfer curve (b). The gate voltage squares the drain current, and a resistor in the source sets the operating point with no extra bias supply. (Schematic, not to scale.)

How the gate controls the current

In an n-channel JFET, current flows through a channel of n-type silicon between drain and source. The gate is p-type material wrapped around that channel; making the gate negative with respect to the source widens the depletion region and squeezes the channel shut. The relationship is Shockley's equation:

I_D = I_DSS × (1 − V_GS / V_P)²

Take a typical small-signal device with I_DSS = 3 mA (the drain current with the gate shorted to the source) and a pinch-off voltage of V_P = −3 V (the gate voltage that closes the channel completely). The curve is a square law:

V_GS = 0 V → 3.00 mA  ·  −0.5 V → 2.08 mA  ·  −1 V → 1.33 mA  ·  −1.5 V → 0.75 mA  ·  −2 V → 0.33 mA  ·  −2.5 V → 0.08 mA  ·  −3 V → 0 mA

Check one value: at V_GS = −1 V, I_D = 3 × (1 − (−1)/(−3))² = 3 × (2/3)² = 3 × 0.444 = 1.33 mA. Because the gate is reverse-biased, its current is only nanoamps — the input resistance of the stage is set by the gate resistor R_G = 1 MΩ, so a sensor sees a 1 MΩ load, not the kilohms a BJT base would present.

Worked example — a self-biased amplifier

Choose the operating point at V_GS = −1 V, so I_D = 1.33 mA. The clever part of self-bias is that the source resistor creates this gate voltage by itself: the drain current flows through R_S, lifting the source above ground, while the gate sits at 0 V through R_G — so the gate is automatically 1 V negative with respect to the source:

R_S = 1 V / 1.33 mA = 750 Ω

The transconductance — how much the drain current changes for a change in gate voltage — comes from the same curve:

g_m = (2 × I_DSS / |V_P|) × (1 − V_GS / V_P) = (2 × 3 / 3) × (2/3) = 1.33 mS

With a drain resistor of R_D = 3.3 kΩ the voltage gain is:

A_v = −g_m × R_D = −1.33 mS × 3.3 kΩ = −4.4

Check the drain voltage: V_DS = 12 − 1.33 mA × (3.3 kΩ + 750 Ω) = 12 − 5.40 = 6.6 V. A 0.5 V peak input gives 2.2 V peak at the output, and the drain swings between 4.4 V and 8.8 V — well clear of the rails, so there is no clipping. The gate voltage swings between −0.5 V and −1.5 V, so the gate stays reverse-biased through the whole cycle. The minus sign in the gain means the output is inverted: when the input rises, the drain current rises, and the drain voltage falls.

The JFET as a voltage-controlled resistor

With a small drain-source voltage the JFET does not saturate — it behaves like a resistor whose value the gate voltage sets. In that ohmic region the resistance is:

r_ds = |V_P| / (2 × I_DSS × (1 − V_GS / V_P))

For our device: V_GS = 0 V → 500 Ω; V_GS = −1 V → 750 Ω; V_GS = −2 V → 1500 Ω. One control voltage sweeps the resistance over a 3:1 range, which is why JFETs are still used as voltage-controlled resistors in automatic-gain-control circuits, electronic volume controls and voltage-controlled attenuators — jobs where a BJT's low input resistance or a MOSFET's gate capacitance would get in the way.

Key points to remember

• The JFET is voltage-controlled: Shockley's equation I_D = I_DSS × (1 − V_GS / V_P)² gives 3.00 mA at V_GS = 0 V and 0 mA at pinch-off, V_P = −3 V.
• Worked example: with I_DSS = 3 mA and V_P = −3 V, a Q point of V_GS = −1 V gives I_D = 1.33 mA, R_S = 750 Ω, g_m = 1.33 mS, gain −4.4 with R_D = 3.3 kΩ, and V_DS = 6.6 V.
• Self-bias needs no extra supply: the drain current through R_S makes the source positive, so the gate is negative with respect to the source by itself.
• The gate draws essentially no current, so R_G = 1 MΩ sets the input resistance — the stage barely loads its source.
• A 0.5 V peak input gives 2.2 V peak out, with the drain swinging 4.4–8.8 V and the gate staying reverse-biased (−0.5 to −1.5 V) — no clipping.
• In the ohmic region the JFET is a voltage-controlled resistor: 500 Ω at V_GS = 0 V, 750 Ω at −1 V, 1500 Ω at −2 V — the basis of AGC and electronic volume circuits.